A debug tool may be used to test functional silicon devices such as a Central Processing Unit (CPU) and an associated chipset that provides the CPU with I/O and memory. More specifically, a conventional debug tool may provide control, internal state visibility and observation of a limited set of signals that are of interest in view of particular code executing on the CPU. The debug tool may support one or more interfaces including these signals, such as a Joint Test Access Group (JTAG) interface and an interface to dedicated control pins (e.g., Probe Mode Break, Probe Mode Ready, etc.).
Conventional debug tools such as the In-Target Probe (ITP) tool implement specific logic and a software control package to manage the tool and to manage interactions between the tool and a System Under Test (SUT). As the number of supported use cases and interactions increases, either the complexity of the logic or the latencies between the software and the SUT increase exponentially. Both outcomes are undesirable, as increased logic complexity entails increased cost and increased latency results in instability in debug operation including but not limited to missing responses.